1. Field of the Invention
The present invention relates generally to integrated circuit implementations of high-speed amplifiers, and more particularly to integrated circuit cascode amplifiers which include feedback or feedforward circuitry for improved amplifier response to rapidly varying input signals.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a conventional high-speed cascode amplifier. The circuit asserts amplified output potential "OUT" (at Node 3) in response to input potential "IN" at the base of NPN bipolar transistor Q2, when biased by bias potentials V.sub.bias and V.sub.2 (with supply voltage Vcc applied across its top and bottom rail). The amplifier of FIG. 1 is typically implemented as an integrated circuit (or portion of an integrated circuit). Such an integrated circuit implementation will be assumed in the following description.
Typically, the output of the FIG. 1 amplifier drives a capacitive load (e.g., the R, G, or B cathode of a CRT color monitor), the supply potential V.sub.cc is in the range 60V to 85V (above ground), bias potential V.sub.2 is in the range from about 8V to 15V above ground, and input potential IN is an analog signal in the range from 0V to 6V above ground. The FIG. 1 amplifier can also drive a resistive load.
The amplifier of FIG. 1 includes a cascode amplifier stage comprising NPN bipolar transistors Q1 and Q2 (connected as shown with the base of Q1 at bias potential V.sub.2, the collector of Q1 at Node 2, the emitter of Q1 connected to the collector of Q2, and the emitter of Q2 connected through resistor R.sub.emitter to ground). Resistor R6 is connected between the top rail and Node 1. Node 1 is maintained at a potential V.sub.bias above Node 2 by circuit element 2.
FIG. 1A is a typical implementation of circuit element 2, which comprises resistors R7 and R8 connected in series between Nodes 1 and 2, and NPN bipolar transistor Q9 connected with its base between resistors R7 and R8 as shown in FIG. 1A. Transistor Q9 provides biasing to output driver transistors Q3 and Q4, to reduce crossover distortion at low signal levels.
NPN bipolar transistor Q3 and PNP bipolar transistor Q4 are emitter followers which buffer the amplifier's output, isolating the amplifier's high output impedance from the load (e.g., from the capacitance of a CRT cathode). Resistor R4 is connected between output node 3 and the emitter of Q3, and resistor R5 is connected between output node 3 and the emitter of Q4. Alternatively, compound emitter followers (such as a Darlington configuration) can be used to drive the amplifier's output.
The feedback path comprising capacitor C1 and resistor R1 between output node 3 and the emitter of transistor Q2 provides positive feedback to improve high frequency performance and to compensate for parasitic capacitance at the output of the cascode amplifier stage. Small capacitor C1 (having typical capacitance 1.1 picoFarads as indicated in FIG. 1) provides additional current into the emitter of cascode transistor Q2, which acts to reinforce the current source action of transistor Q2 at high frequencies.
We next describe the operation of the FIG. 1 amplifier. In response to an increase in the input potential IN, the collector current of Q2 increases, and thus the collector current I.sub.C of Q1 increases and the current through resistor R6 increases. Thus, the potentials at Nodes 1 and 2 fall, the emitter potentials of Q3 and Q4 fall, and thus the output potential OUT at Node 3 falls. At the same time, feedback current I.sub.F flows from the emitter of Q2 through resistor R1 to capacitor C1. Thus, the current I.sub.F provides positive feedback, which increases the total current I.sub.C flowing into the collector of transistor Q1 (above the value it would have if R1 were replaced by an open circuit).
In response to a decrease in the input potential IN of the FIG. 1 amplifier, the collector current of Q2 decreases, and thus the collector current I.sub.C of Q1 decreases and the current through resistor R6 decreases. Thus, the potentials at Nodes 1 and 2 rise, the emitter potentials of Q3 and Q4 rise, and thus the output potential OUT at Node 3 rises. At the same time, feedback current I.sub.F flows to the emitter of Q2 from capacitor C1 through resistor R1. The current I.sub.F provides positive feedback, which decreases the total current I.sub.C flowing into the collector of Q1 (below the value it would have if R1 were replaced by an open circuit).
However, the amount of positive feedback (i.e., the amplitude of current I.sub.F) needed by the FIG. 1 amplifier to achieve a given level of overshoot in the output OUT (in response to a rising or falling edge of input IN) is different for a rising edge than for a falling edge of the output OUT. This asymmetry is apparent from FIG. 2.
In FIG. 2, the vertical axis represents the output potential OUT (in volts) produced in response to a square wave input signal (having period 40 nsec). The horizontal axis represents time (from t=0 to t=80 nsec). Curve X assumes a value of capacitance for capacitor C1 which optimizes (minimizes) the fall time for the output potential (in response to a rising edge of the input potential), and curve Y assumes a lesser capacitance for capacitor C1 which optimizes (minimizes) the overshoot of the output potential in response to a rising or falling edge of the input potential).
As apparent from FIG. 2, in order to minimize fall time of the output potential, substantial overshoot must be tolerated at both the rising and falling edges of the output potential. The overshoot at each falling edge of the output potential is about 5%, and the overshoot at each rising edge of the output potential is significantly greater (about 12%).
When the capacitance of C1 is sufficiently reduced to minimize overshoot (as represented by curve Y, with only about 5% overshoot at each rising edge and no overshoot at each falling edge of the output potential), long rise and fall times must be tolerated.
It would be desirable to implement an integrated circuit cascode amplifier (with feedback circuitry for improved amplifier response to rapidly varying input) such that the feedback circuitry allows both rise and fall times of the output (in response to falling and rising edges of the input) to be minimized, with no more than a tolerably small overshoot at the rising edges as well as falling edges of the output potential, and preferably with at least substantially equal overshoot at the rising and falling edges of the output potential. Until the present invention, it had not been known how to do so.